Apr/physical Design Engineer

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On-site
Chip/block level floorplan
Clock tree synthesis
Familiar with apr tools
The role involves chip/block level floorplan and clock tree synthesis

Job Summary

  • The role involves chip/block level floorplan and clock tree synthesis.
  • Candidates should be experienced in digital design and APR chip implementation.
  • Familiarity with advanced process nodes and scripting languages is essential.

Matching Summary

The role involves chip/block level floorplan and clock tree synthesis.

Skills & Requirements

Must-have

  • Chip/Block level floorplan
  • Clock tree synthesis
  • Familiar with APR tools

Nice-to-have

  • Good customer-oriented attitude
  • Good command of Japanese
  • Self-motivated candidates welcome

Key Requirements

  • BCH degree and above in EE/CS
  • Experienced in advanced process nodes
  • Good command of Japanese

Work Rights

Not specified

Tailored Resume

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