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Renesas is seeking a Graduate Digital Engineer to engage in digital design and RTL coding, focusing primarily on Verilog or System Verilog. The ideal candidate will have a strong educational background in Electrical or Electronics Engineering, and hands-on experience with the full design cycle in VLSI digital design.
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Job Summary
The role involves responsible digital design and RTL coding using Verilog or SystemVerilog within a full design cycle.
Renesas offers a flexible hybrid work model allowing two days of remote work per week alongside team collaboration.
Candidates will validate digital design functionality on silicon and develop scripts to automate frequently used processes.
Matching Summary
Match Score: 75
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Renesas is seeking a Graduate Digital Engineer to engage in digital design and RTL coding, focusing primarily on Verilog or System Verilog. The ideal candidate will have a strong educational background in Electrical or Electronics Engineering, and hands-on experience with the full design cycle in VLSI digital design.
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Skills & Requirements
Must-have
MS in Electronics or Electrical Engineering
HDL experience with Verilog or SystemVerilog
Full digital IC design cycle knowledge
Scripting skills in TCL or Perl
Proficiency in Unix/Linux environments
Nice-to-have
Exposure to industry standard VLSI tools
Experience with CDC, Lint, STA, DFT
Strong logical reasoning abilities
Quick learner with good communication skills
Innovative problem-solving mindset
Key Requirements
Master's degree in Electronics or Electrical Engineering