Digital IC Design Engineer (RTL/Verilog/Logic Synthesis/Frontend) LT95
TRUST RECRUIT PTE. LTD.
Singapore
Verilog/vhdl rtl design experience
Logic synthesis and static timing analysis
Full ic design cycle from rtl to tape-out
The role involves developing and implementing Verilog/VHDL RTL designs based on product specifications while performing logic synthesis and static timing analysis
Job Summary
The role involves developing and implementing Verilog/VHDL RTL designs based on product specifications while performing logic synthesis and static timing analysis.
Candidates will collaborate with physical design teams to achieve timing closure and lead Design-for-Test activities including scan insertion and ATPG.
The position requires supporting production by working with test teams to debug functional issues in post-silicon devices.
Matching Summary
Match Score: 75
The role involves developing and implementing Verilog/VHDL RTL designs based on product specifications while performing logic synthesis and static timing analysis.
Skills & Requirements
Must-have
Verilog/VHDL RTL design experience
Logic synthesis and static timing analysis
Full IC design cycle from RTL to tape-out
DFT methodologies including scan insertion and ATPG
5 years of digital IC design experience
Nice-to-have
Experience with USB, UART, SPI, I2C protocols
FPGA-based verification and validation skills
Post-silicon debug and test issue resolution
Knowledge of Cadence or Synopsys EDA tools
Cross-functional collaboration in design reviews
Key Requirements
Degree or Master's in Electrical/Electronic Engineering
At least 5 years of relevant experience in digital IC design
Proven experience in full IC design cycle (RTL to tape-out)