Product Soc Architect

Inteelabs

Santa Clara, California, United States
Base: $190,610.00-311,890.00 usd; bonus/equity: st...
**
8+ years soc or cpu architecture experience
Networking performance engineering expertise
High-speed ethernet and packet processing
** Inteelabs is seeking a Senior IPU SoC Architect in Santa Clara, California, to lead architectural development for cutting-edge Infrastructure Processing Unit (IPU) and Data Processing Unit (DPU) platforms. The role requires extensive experience in SoC architecture, performance engineering, and networking technologies, along with strong leadership capabilities. **

Job Summary

  • This strategic role involves defining the architectural vision for next-generation Infrastructure Processing Unit (IPU) and Data Processing Unit (DPU) platforms.
  • The successful candidate will lead comprehensive architecture development from initial concept through silicon implementation while ensuring optimal end-to-end performance.
  • Intel offers a competitive total compensation package including stock bonuses, health benefits, retirement plans, and a hybrid work model.

Matching Summary

Match Score: 75

** Inteelabs is seeking a Senior IPU SoC Architect in Santa Clara, California, to lead architectural development for cutting-edge Infrastructure Processing Unit (IPU) and Data Processing Unit (DPU) platforms. The role requires extensive experience in SoC architecture, performance engineering, and networking technologies, along with strong leadership capabilities. **

Salary

Base: $190,610.00-311,890.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, vacation programs

Skills & Requirements

Must-have

  • 8+ years SoC or CPU architecture experience
  • Networking performance engineering expertise
  • High-speed Ethernet and packet processing
  • Memory subsystem architecture design
  • Virtualization architecture SMMU/IOMMU

Nice-to-have

  • Post Graduate degree in STEM field
  • ARM/x86 NUMA system experience
  • IPU/SmartNIC accelerator SoC background
  • PCIe CXL memory semantics familiarity
  • Multi-generation architectural ownership

Key Requirements

  • Bachelor's degree in Electrical or Computer Engineering
  • 8+ years of SoC/CPU/subsystem architecture leadership
  • Experience with high-speed Ethernet and data center networking

Work Rights

Not specified

Tailored Resume

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