This role involves leading the implementation of Hardware Design-for-Test features to support ATE, in-system test, and diagnostics for complex networking chips
Job Summary
This role involves leading the implementation of Hardware Design-for-Test features to support ATE, in-system test, and diagnostics for complex networking chips.
The candidate will drive DFT requirements early in the design cycle while collaborating with front-end RTL and backend physical design teams.
Join a global team shaping Cisco's ground-breaking Silicon One architecture by crafting innovative next-generation silicon device models.
Matching Summary
This role involves leading the implementation of Hardware Design-for-Test features to support ATE, in-system test, and diagnostics for complex networking chips.
Skills & Requirements
Must-have
10+ years ASIC DFT experience
Jtag protocols and Scan architecture
Memory BIST and boundary scan
ATPG and EDA tool proficiency
Gate level simulation debugging
Post-silicon validation expertise
Tcl and Python scripting skills
Nice-to-have
Verilog design for custom DFT logic
DFT CAD development methodology
Test Static Timing Analysis
System Verilog Logic Equivalency checking
Collaboration with multi-functional teams
Minimal mentorship capability
Key Requirements
Bachelor's or Master's Degree in Electrical or Computer Engineering
Minimum 10 years of relevant industry experience
Experience with TestMax, Tetramax, Tessent, and PrimeTime tools