Principal Design Engineer

NXP India Pvt. Ltd.

Noida, India
Rtl design verilog/systemverilog
Frontend sign-off tools
Asic design flows
Lead the architectural definition, micro-architecture, and detailed design of complex systems on chip (SoCs)

Job Summary

  • Lead the architectural definition, micro-architecture, and detailed design of complex systems on chip (SoCs).
  • Drive the entire design flow from specification to tape-out, including RTL design, solid knowledge of Frontend Sign-off tools.
  • Mentor and provide technical guidance to junior and senior design engineers, fostering a culture of continuous learning and technical excellence.

Matching Summary

Lead the architectural definition, micro-architecture, and detailed design of complex systems on chip (SoCs).

Skills & Requirements

Must-have

  • RTL design Verilog/SystemVerilog
  • Frontend Sign-off tools
  • ASIC design flows
  • EDA tools Synopsys Cadence
  • complex systems on chip (SoCs)

Nice-to-have

  • technical leadership and mentoring
  • innovative design methodologies
  • strategic roadmap discussions
  • embedded processors integration
  • communication protocols knowledge

Key Requirements

  • 10+ years digital IC design experience
  • Bachelor's or Master's degree
  • Proven expertise in Verilog/SystemVerilog
  • Deep understanding of ASIC design flows
  • Extensive experience with industry-standard EDA tools

Work Rights

Not specified

Tailored Resume

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