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Analog Devices, Inc. is seeking a Senior DFT Engineer with expertise in ASIC/SoC DFT methodologies to support various product lines. The ideal candidate should possess strong technical skills in DFT architecture, automation, and verification, while mentoring junior team members.
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Job Summary
The role involves designing DFT specifications and implementing state-of-the-art methodologies to drive advancements in digitized factories and digital healthcare.
Candidates must deliver high-quality verified ATPG patterns and support pre/post silicon verification and debug processes independently.
This position requires expert-level knowledge of Scan, Test Compression, At-Speed Test, MBIST, and LBIST within a global semiconductor leader.
Matching Summary
Match Score: 75
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Analog Devices, Inc. is seeking a Senior DFT Engineer with expertise in ASIC/SoC DFT methodologies to support various product lines. The ideal candidate should possess strong technical skills in DFT architecture, automation, and verification, while mentoring junior team members.
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Skills & Requirements
Must-have
6-8 years ASIC SoC DFT experience
Expert Tessent DFT tool knowledge
Scan insertion and compression expertise
ATPG pattern generation skills
Perl Python Tcl scripting ability
Nice-to-have
Cadence Synopsys DFT tool experience
Low power scan and UPF knowledge
Strong written verbal communication
Mentoring junior team members
JTAG IEEE 1149 standard familiarity
Key Requirements
6-8 years directly related ASIC SoC DFT experience
Expert level knowledge of DFT architecture and planning
Hands-on experience with Tessent DFT tools
Gate-level simulation with SDF capability
Silicon test bring up support experience
Work Rights
Must have US citizenship, PR, or protected individual status