Altera is seeking a System & Architecture Engineer to define and develop the next generation of high-speed SerDes and PHY technology
Job Summary
Altera is seeking a System & Architecture Engineer to define and develop the next generation of high-speed SerDes and PHY technology.
Responsibilities include modeling, designing, and optimizing system architectures, defining requirements, and developing DSP algorithms.
The role involves collaborating with development teams and stakeholders to ensure scalability, reliability, and performance of advanced semiconductor solutions.
Matching Summary
Altera is seeking a System & Architecture Engineer to define and develop the next generation of high-speed SerDes and PHY technology.
Skills & Requirements
Must-have
SerDes and PHY design expertise
System modeling tools (Matlab, Simulink)
DSP algorithm development
Communication standards knowledge
Serial link optimization
Nice-to-have
Analog design familiarity
RTL development familiarity
Firmware development familiarity
Post-silicon validation experience
Key Requirements
8+ years FPGA/ASIC architecture, design, development
B.Sc. or M.Sc. Electrical Engineering
Proven SerDes and PHY design expertise
Hands-on system modeling and DSP algorithm development
Strong communication standards understanding
Experience optimizing serial link chip implementations