Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
Job Summary
Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
Matching Summary
Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Skills & Requirements
Must-have
Hardware Design-for-Test (DFT) features
ATE, in-system test, debug and diagnostics
Jtag protocols, Scan and BIST architectures
ATPG and EDA tools like TestMax
Gate level simulation, debugging with VCS
Post-silicon validation and debug experience
Scripting skills: Tcl, Python/Perl
Nice-to-have
innovative DFT IP development
groundbreaking next generation networking chips
thrive in a multifaceted environment
crafting groundbreaking solutions
Key Requirements
Bachelor's or Master’s Degree in Electrical or Computer Engineering
at least 10 years of experience
Knowledge of latest innovative trends in DFT
Experience with memory BIST and boundary scan
Experience with Tetramax, Tessent tool sets, PrimeTime