Asic - Signal And Power Integrity Technical Leader - 10 To 16 Years - Bangalore/chennai

Cisco UK

Bangalore, India
10+ years signal and power integrity experience
56g pam4 and above high-speed serdes expertise
Keysight ads ansys hfss cadence apd proficiency
This role involves leading a specialized team to define, design, and verify next-generation ASIC packaging for Cisco's Silicon One architecture

Job Summary

  • This role involves leading a specialized team to define, design, and verify next-generation ASIC packaging for Cisco's Silicon One architecture.
  • The successful candidate will develop design rules for ultra-high-speed signaling while ensuring power, performance, and area goals are met across interposer and substrate platforms.
  • Join a highly specialized team with experts in advanced IC package design and heterogeneous system integration using the latest 2.5D fanout technologies.

Matching Summary

This role involves leading a specialized team to define, design, and verify next-generation ASIC packaging for Cisco's Silicon One architecture.

Skills & Requirements

Must-have

  • 10+ years signal and power integrity experience
  • 56G PAM4 and above high-speed SerDes expertise
  • Keysight ADS Ansys HFSS Cadence APD proficiency
  • Multiple high-speed ASIC tape-out package experience
  • Transmission line theory and electromagnetics knowledge

Nice-to-have

  • Experience leading small to medium technical teams
  • Advanced node packaging (5nm 3nm) background
  • High-bandwidth memory HBM interface SI experience
  • Die-to-die interfaces UCIe or proprietary knowledge
  • MATLAB or Python scripting skills

Key Requirements

  • Bachelor's degree in Electrical Engineering with 10+ years experience
  • Master's degree in Electrical Engineering with 8+ years experience
  • PhD in Electrical Engineering with 5+ years experience
  • Proven track record of multiple high-speed ASIC tape-outs

Work Rights

Not specified

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