Senior Soc Physical Design/power Analysis/rdl Engineer

Altera Corporation

San Jose, California, United States
Base: $127,400 - $184,400 usd; bonus/equity: incen...
Physical design implementation experience
Static and dynamic power integrity analysis
Bump/rdl/mimcap planning expertise
The role involves performing physical design implementation and power integrity static and dynamic analysis for SoC block level and subsystem level

Job Summary

  • The role involves performing physical design implementation and power integrity static and dynamic analysis for SoC block level and subsystem level.
  • Candidates must possess multiple tape-out experiences in deep submicron process nodes with extensive hands-on knowledge of physical design flows.
  • The position offers a salary range of $127,400 to $184,400 USD for the Bay Area California location.

Matching Summary

The role involves performing physical design implementation and power integrity static and dynamic analysis for SoC block level and subsystem level.

Salary

Base: $127,400 - $184,400 USD; Bonus/Equity: Incentive opportunities based on performance; Benefits: Not specified

Skills & Requirements

Must-have

  • Physical design implementation experience
  • Static and dynamic power integrity analysis
  • BUMP/RDL/MIMCAP planning expertise
  • Deep submicron process node tape-out experience
  • STA LEC ERC DRC signoff flow knowledge

Nice-to-have

  • Low power design methodologies
  • Mentoring junior team members
  • Scripting languages Perl TCL Python
  • Hardware description languages VHDL Verilog
  • Design optimization for power frequency area

Key Requirements

  • Bachelor's degree in computer or electronic engineering
  • 5+ years of relevant experience in physical design
  • Multiple tape-out experience in deep submicron nodes
  • Hands-on expertise with Perl TCL Python scripting

Work Rights

Not specified

Tailored Resume

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