Asic Verification Engineer - Clocks

NVIDIA

Hybrid
System verilog
Uvm
Constraint random verification
The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in SOC automotive and datacenter ASICs

Job Summary

  • The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in SOC automotive and datacenter ASICs.
  • Own validation of Clocking structures in Tegra automotive and datacenter products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
  • We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast.

Matching Summary

The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in SOC automotive and datacenter ASICs.

Skills & Requirements

Must-have

  • System Verilog
  • UVM
  • constraint random verification
  • coverage metrics
  • clocking and reset logic
  • pre-silicon platforms

Nice-to-have

  • creative, curious, and motivated
  • passion for technology
  • artificial intelligence

Key Requirements

  • 3+ years of relevant industry work experience
  • BS or MS in EE/ECE or equivalent experience
  • Expertise in industry-standard verification flows
  • Exposure on block level and system-level verification
  • Strong coding skills in System Verilog, scripting languages (Perl/python) and C++

Work Rights

Not specified

Tailored Resume

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