Physical Design Engineer (place & Route)

Astera Labs

San Jose, California, United States
Base: $160,000 - $195,000 (staff) or $203,000 - $2...
On-site
8+ years soc physical design experience
7nm or less technology node expertise
Cadence or synopsys tool proficiency
Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies

Job Summary

  • Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.
  • This generalist physical design role requires broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off to drive blocks from RTL to GDSII.
  • The position offers a base salary range of $160,000 to $230,000 depending on level, along with equity and benefits eligibility.

Matching Summary

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

Salary

Base: $160,000 - $195,000 (Staff) or $203,000 - $230,000 (Principal); Bonus/Equity: Eligible for equity; Benefits: Eligible for benefits

Skills & Requirements

Must-have

  • 8+ years SoC physical design experience
  • 7nm or less technology node expertise
  • Cadence or Synopsys tool proficiency
  • Timing closure and signoff methodology
  • Tcl Python or Perl scripting skills

Nice-to-have

  • Design for test DFT knowledge
  • High-speed SERDES integration experience
  • PCIe CXL Ethernet protocol familiarity
  • ECO methodologies and tools
  • Clock tree synthesis optimization

Key Requirements

  • Bachelor's degree in EE required Master's preferred
  • 8+ years supporting complex SoC products
  • Block level ownership from architecture to GDSII
  • Full-time on-site work requirement in San Jose

Work Rights

Not specified

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