Fpga Digital Design And Verification Engineer-contract

Altera

San Jose, California, United States
Base: $100-105k usd (bay area); bonus/equity: ince...
Risc-v design experience
Systemverilog and verilog proficiency
Uvm-based verification environments
This 6-month contract role offers hands-on experience designing and verifying next-generation FPGA products using RISC-V architecture

Job Summary

  • This 6-month contract role offers hands-on experience designing and verifying next-generation FPGA products using RISC-V architecture.
  • Candidates will develop self-checking testbenches and constrained-random tests while collaborating with experienced engineers on system-level features.
  • The position requires debugging RTL failures and analyzing simulations using industry-standard EDA tools in a Linux-based environment.

Matching Summary

This 6-month contract role offers hands-on experience designing and verifying next-generation FPGA products using RISC-V architecture.

Salary

Base: $100-105K USD (Bay Area); Bonus/Equity: Incentive opportunities available; Benefits: Not specified

Skills & Requirements

Must-have

  • RISC-V design experience
  • SystemVerilog and Verilog proficiency
  • UVM-based verification environments
  • Constrained random verification skills
  • Simulation tools like VCS or QuestaSim

Nice-to-have

  • Experience with AXI protocol verification
  • Knowledge of Intel Quartus Prime or Vivado
  • Python, Perl, Tcl, or C scripting skills
  • Exposure to AI/ML hardware acceleration
  • Formal verification concepts knowledge

Key Requirements

  • Bachelor's Degree in Computer or Electrical Engineering
  • 1+ years experience in Digital Logic Design
  • Eligibility for U.S. export authorizations

Work Rights

Must be eligible for U.S. export authorizations

Tailored Resume

Cover Letter