Senior Verification Engineer - Cisco Silicon One

Cisco

Caesarea, Israel
Advanced verification environments
Systemverilog and uvm
Debug skills pre-silicon and in-lab
Join the Cisco Silicon One Front-End Design Verification team responsible for validating advanced networking silicon

Job Summary

  • Join the Cisco Silicon One Front-End Design Verification team responsible for validating advanced networking silicon.
  • Develop advanced verification environments and ensure functional coverage.
  • Collaborate with various teams to achieve design closure and enhance productivity.

Matching Summary

Join the Cisco Silicon One Front-End Design Verification team responsible for validating advanced networking silicon.

Skills & Requirements

Must-have

  • Advanced verification environments
  • SystemVerilog and UVM
  • Debug skills pre-silicon and in-lab

Nice-to-have

  • Scripting skills in Python or Perl
  • Experience with system-level integration
  • Basic software and design knowledge

Key Requirements

  • 6+ years of experience in digital logic design verification
  • Advanced knowledge of SystemVerilog and UVM

Work Rights

Not specified

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