Senior Asic Verification Engineer

Cisco

Egypt
System verilog and uvm methodology
Design verification testbench development
Functional coverage and constrained random verification
Cisco Common ASIC Group develops next generation switching systems with complex ASIC chips using cutting-edge technologies

Job Summary

  • Cisco Common ASIC Group develops next generation switching systems with complex ASIC chips using cutting-edge technologies.
  • The role involves creating and maintaining test benches, performing end-to-end verification, and collaborating closely with design and hardware teams.
  • Cisco offers a collaborative team environment with opportunities for professional growth and innovation in chip design.

Matching Summary

Cisco Common ASIC Group develops next generation switching systems with complex ASIC chips using cutting-edge technologies.

Skills & Requirements

Must-have

  • System Verilog and UVM methodology
  • Design verification testbench development
  • Functional coverage and constrained random verification
  • Scripting with Python, Perl, shell
  • ASIC verification in simulation and emulation

Nice-to-have

  • C/C++ programming knowledge
  • Experience with Formal Verification
  • Familiarity with Perforce/Git
  • Collaboration with design and hardware teams
  • Emulation testing experience

Key Requirements

  • Completed degree in Electrical or Computer Engineering
  • At least 8 years of design verification experience
  • Proficient in System Verilog, Assertions, and UVM
  • Experience in functional coverage and constrained random environments
  • Scripting experience in Python, Perl, or shell

Work Rights

Not specified

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