This role involves driving high-quality Design for Test (DFT) verification to ensure robust silicon solutions for Cisco's core networking products
Job Summary
This role involves driving high-quality Design for Test (DFT) verification to ensure robust silicon solutions for Cisco's core networking products.
You will collaborate closely with Front-end RTL and backend physical design teams to deeply understand chip architecture and integrate sub-systems.
The position offers the opportunity to contribute to groundbreaking solutions shaping the future of networking silicon within a collaborative innovation environment.
Matching Summary
This role involves driving high-quality Design for Test (DFT) verification to ensure robust silicon solutions for Cisco's core networking products.
Skills & Requirements
Must-have
5+ years ASIC digital design experience
Proficient in Verilog/SystemVerilog coding
Experience with front-end tools and synthesis
Scripting proficiency in Python, Tcl, or Make
Fluency in English spoken and written
Nice-to-have
Familiarity with AMBA interface protocols
Knowledge of power optimization and UPF
Experience with DFT/MBIST methodologies
Strong communication and self-motivation skills
Collaborative team environment participation
Key Requirements
5+ years industry experience in ASIC digital design