$127,400 - $184,400 usd; not specified; not specif...
Physical design implementation
Power integrity static and dynamic analysis
Bump/rdl/mimcap planning
Performs Physical Design Implementation and Power Integrity Static and Dynamic Analysis for SoC block level and Subsystem level
Job Summary
Performs Physical Design Implementation and Power Integrity Static and Dynamic Analysis for SoC block level and Subsystem level.
Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, static timing analysis, and power/clock distribution.
Possesses design optimization knowledge to improve product-level parameters such as power, frequency, and area.
Matching Summary
Performs Physical Design Implementation and Power Integrity Static and Dynamic Analysis for SoC block level and Subsystem level.
Salary
$127,400 - $184,400 USD; Not specified; Not specified
Skills & Requirements
Must-have
Physical Design Implementation
Power Integrity Static and Dynamic Analysis
BUMP/RDL/MIMCAP planning
Physical design signoff flow
Scripting languages Perl, TCL, Python
VHDL and Verilog
Nice-to-have
Low power design methodologies
Mentoring junior team members
Strong initiative and analytical skills
Team working and multitasking ability
Key Requirements
5+ years of relevant experience
Multiple tape-out experience
Deep submicron process nodes knowledge
Physical design flow and EDA tools expertise
Physical design signoff flow expertise
Bachelor's degree in computer engineering, electronic Engineering or related field