Senior Soc Timing Engineer

Altera

Penang, Malaysia
Static timing analysis expertise
Primetime ptpx tool proficiency
Timing constraints development in tcl
The candidate will be responsible for the timing closure and signoff of FPGA, SoC, and Subsystem timing

Job Summary

  • The candidate will be responsible for the timing closure and signoff of FPGA, SoC, and Subsystem timing.
  • This role involves working closely with design, architecture, and physical design teams to ensure timing convergence.
  • Candidates must possess a BE/MS/PhD in Electronics/Electrical Engineering with at least 7 years of experience.

Matching Summary

The candidate will be responsible for the timing closure and signoff of FPGA, SoC, and Subsystem timing.

Skills & Requirements

Must-have

  • Static timing analysis expertise
  • Primetime PTPX tool proficiency
  • Timing constraints development in TCL
  • Python scripting skills
  • Physical design flow knowledge

Nice-to-have

  • Strong communication skills
  • Problem solving abilities
  • Analytical thinking capabilities

Key Requirements

  • BE/MS/PhD in Electronics or Electrical Engineering
  • 7+ years of experience in timing closure and signoff
  • Experience with 10nm or lower technology nodes

Work Rights

Not specified

Tailored Resume

Cover Letter