Senior Soc Physical Design/power Analysis/rdl Engineer

Altera

San Jose, California, United States
Base: $127,400 - $184,400 usd; bonus/equity: incen...
Physical design implementation flow
Bump/rdl/mimcap planning expertise
Static timing analysis signoff
The role involves performing physical design implementation and power integrity static and dynamic analysis for SoC block and subsystem levels

Job Summary

  • The role involves performing physical design implementation and power integrity static and dynamic analysis for SoC block and subsystem levels.
  • Candidates must possess extensive hands-on experience with deep submicron process nodes and multiple tape-outs.
  • The position offers a salary range of $127,400 to $184,400 USD for the Bay Area California location.

Matching Summary

The role involves performing physical design implementation and power integrity static and dynamic analysis for SoC block and subsystem levels.

Salary

Base: $127,400 - $184,400 USD; Bonus/Equity: Incentive opportunities available; Benefits: Not specified

Skills & Requirements

Must-have

  • Physical design implementation flow
  • BUMP/RDL/MIMCAP planning expertise
  • Static timing analysis signoff
  • Deep submicron process nodes experience
  • Perl TCL Python scripting skills

Nice-to-have

  • Low power design methodologies
  • Mentoring junior team members
  • Multiple tape-out experience
  • Design optimization knowledge
  • Flow automation development

Key Requirements

  • Bachelor's degree in computer or electronic engineering
  • 5+ years relevant experience in physical design
  • Hands-on expertise with EDA tools and scripting languages

Work Rights

Not specified

Tailored Resume

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