Sr. Principal Engineer -sta

NXP Semiconductors

**
Expertise in soc io constraints
Advanced timing analysis and debug
Hands-on experience with technology nodes
** NXP Semiconductors is seeking a Sr. Principal Engineer specializing in Static Timing Analysis (STA) to lead timing closure and design changes for System-on-Chip (SOC) projects. The ideal candidate will have extensive experience in advanced digital design architectures, timing analysis, and EDA tools across multiple technology nodes. **

Job Summary

  • This role involves driving timing signoff criteria and design clocking.
  • You will interface with critical domains like IP, Functional Integration, and DFT.
  • The position requires expertise in ECO creation and timing convergence.

Matching Summary

Match Score: 75

** NXP Semiconductors is seeking a Sr. Principal Engineer specializing in Static Timing Analysis (STA) to lead timing closure and design changes for System-on-Chip (SOC) projects. The ideal candidate will have extensive experience in advanced digital design architectures, timing analysis, and EDA tools across multiple technology nodes. **

Skills & Requirements

Must-have

  • Expertise in SOC IO constraints
  • Advanced Timing Analysis and Debug
  • Hands-on experience with technology nodes

Nice-to-have

  • Understanding of advanced digital design architectures
  • Knowledge of EDA tools
  • Contribution in flow/methodology related scripting

Key Requirements

  • Experience with technology nodes like 28nm to 7nm
  • Ability to manage Functional/Scan/MBIST timing constraints
  • Knowledge about SDF and GLS

Work Rights

Not specified

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