Job Summary

• Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
• Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
• Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.

Matching Summary

Skills & Requirements

Key Requirements

• 9+ years of experience
• Bachelor's or Master's degree
• Verilog or VHDL
• UVM-based testbenches

Work Rights