Emir/esd Engineer

Cisco UK

Bachelor's or master's degree in electrical engineering
3 years hands-on experience in asic design
Strong understanding of schematics and layout in finfet technologies
The role involves performing comprehensive chip-level EMIR and ESD analysis to ensure the reliability of next-generation designs

Job Summary

  • The role involves performing comprehensive chip-level EMIR and ESD analysis to ensure the reliability of next-generation designs.
  • Engineers will collaborate with package teams and block owners to guide design fixes and ensure robust power grid performance.
  • The team is dedicated to driving advancements in power, performance, and reliability while building the foundation for the future of connectivity.

Matching Summary

The role involves performing comprehensive chip-level EMIR and ESD analysis to ensure the reliability of next-generation designs.

Skills & Requirements

Must-have

  • Bachelor's or Master's degree in Electrical Engineering
  • 3 years hands-on experience in ASIC design
  • Strong understanding of schematics and layout in FinFET technologies
  • Experience in deep submicron CMOS technologies
  • Hands-on RTL-to-GDSII flow, floorplanning, and power planning

Nice-to-have

  • Good knowledge of ESD protection concepts
  • Familiarity with Synopsys, Cadence, or Siemens tools
  • Strong scripting skills in Python, TCL, or Bash
  • Ability to collaborate effectively with cross-functional teams
  • Experience in full-chip physical design and tape-out processes

Key Requirements

  • Minimum 3 years of hands-on experience in ASIC design and verification
  • Degree in Electrical Engineering or Computer Science
  • Experience with RTL-to-GDSII flow and floorplanning

Work Rights

Not specified

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