Jr.pd

Qualitest Group

Bangalore, India
On-site
Physical design tasks
Timing closure using sta tools
Ir drop and em analysis
You will be responsible for implementing and optimizing the physical layout of complex ASICs from RTL to GDSII

Job Summary

  • You will be responsible for implementing and optimizing the physical layout of complex ASICs from RTL to GDSII.
  • You’ll collaborate closely with RTL design, verification, and DFT teams to ensure successful tape-out of high-performance, low-power silicon designs.
  • Contribute to flow development and automation to improve quality and efficiency.

Matching Summary

You will be responsible for implementing and optimizing the physical layout of complex ASICs from RTL to GDSII.

Skills & Requirements

Must-have

  • physical design tasks
  • timing closure using STA tools
  • IR drop and EM analysis
  • physical verification (LVS/DRC)
  • low power complex chip designs

Nice-to-have

  • hierarchical design methodologies
  • advanced nodes (5nm or below)
  • low power design techniques (UPF)

Key Requirements

  • 5+ to 8 years of experience
  • B.E in Electronics/ M.Tech in VLSI Engineering
  • proven tape-out record
  • Strong hands-on experience with industry-standard tools
  • Good scripting skills (TCL, Python, or Perl)

Work Rights

Not specified

Tailored Resume

Cover Letter