Asic Design Verification Engineer | Uvm | Exp- 8+ Years

Cisco

Bangalore, India
Asic verification using uvm/system verilog
Develop test plans and tests
Collaborate closely with designers
You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams

Job Summary

  • You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams.
  • Your impact will contribute to developing Cisco’s progressive data center solutions.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations.

Matching Summary

You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams.

Skills & Requirements

Must-have

  • ASIC verification using UVM/System Verilog
  • Develop test plans and tests
  • Collaborate closely with designers

Nice-to-have

  • Experience with Forwarding logic
  • Knowledge of formal verification
  • Demonstrated ability on protocols

Key Requirements

  • Bachelor’s or master’s degree in EE or CE
  • 7+ years of ASIC design verification experience
  • Scripting experience with Perl and/or Python

Work Rights

Not specified

Tailored Resume

Cover Letter