Base: $100k - $500k; bonus/equity: not specified; ...
On-site
Scan compression and insertion
Memory bist and repair schemes
Jtag/ijtag
You will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors
Job Summary
You will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors.
This role requires a good understanding of both Design for Test (DFT) architecture and implementation, as well as comprehensive expertise in Static Timing Analysis (STA) for complex SoCs.
We value collaboration, curiosity, and a commitment to solving hard problems.
Matching Summary
You will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors.
Salary
Base: $100k - $500k; Bonus/Equity: Not specified; Benefits: Not specified
Skills & Requirements
Must-have
Scan Compression and insertion
Memory BIST and repair schemes
JTAG/IJTAG
at-speed test methodologies
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Static Timing Analysis tools
Verilog/SystemVerilog RTL coding
Nice-to-have
collaboration
curiosity
solving hard problems
AI passion
RISC-V CPU development
Key Requirements
Experience in Verilog/SystemVerilog RTL coding
Eligibility to access U.S. export-controlled technology
Work Rights
Eligibility to access U.S. export-controlled technology