Principal Engineer, Design Verification Engineering
Analog Devices
Dublin, Ireland
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Systemverilog/uvm testbenches
Constrained-random stimulus
Coverage closure
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Analog Devices is seeking a Principal Engineer for Design Verification Engineering in Dublin, Ireland. The role involves leading the verification of mixed-signal power converter controllers and requires extensive experience in IC design verification, specifically with SystemVerilog/UVM.
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Job Summary
Provide technical leadership for design verification of mixed-signal power converter controllers from architecture through silicon bring-up.
Develop and review SystemVerilog/UVM testbenches for digital and AMS verification, leveraging reusable verification components.
Partner with design evaluation and applications teams to support silicon bring-up, correlate simulation to lab results, and root-cause issues.
Matching Summary
Match Score: 75
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Analog Devices is seeking a Principal Engineer for Design Verification Engineering in Dublin, Ireland. The role involves leading the verification of mixed-signal power converter controllers and requires extensive experience in IC design verification, specifically with SystemVerilog/UVM.
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Skills & Requirements
Must-have
SystemVerilog/UVM testbenches
constrained-random stimulus
coverage closure
AMS verification
silicon bring-up support
Nice-to-have
AI tools for verification
power management domain knowledge
continuous learning opportunities
Key Requirements
12+ years of relevant experience in IC design verification
Proven technical leadership delivering verification for multiple ICs