Job Summary

• The role focuses on creating software models using C++, scripting languages, and Verilog/VHDL for hardware blocks.
• Candidates will be responsible for running verification and simulation processes using Verilog and VHDL.
• Training will be provided to help interns acquire the necessary knowledge and skillset for the position.

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Skills & Requirements

Key Requirements

• Minimum Bachelor's or Master's Degree in Electronics/Software Engineering
• Must be a student or intern eligible for fixed-term employment

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