Base: $183,800.00 to $263,600.00; bonus/equity: no...
Design-for-test expertise
Jtag protocols experience
Dft requirements management
You will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle
Job Summary
You will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.
As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era and beyond.
Matching Summary
You will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.
Salary
Base: $183,800.00 to $263,600.00; Bonus/Equity: Not specified; Benefits: Medical, dental and vision insurance
Skills & Requirements
Must-have
Design-for-Test expertise
JTAG protocols experience
DFT requirements management
Nice-to-have
Verilog design experience
collaborative team environment
innovative problem solving
Key Requirements
Bachelor's or Master’s Degree in Electrical or Computer Engineering