Sr Education Application Engineer

Cadence

Not specified (could be hybrid based on typical practices for similar roles).
Systemverilog coding experience
Uvm methodology projects
Low-power simulation exposure
Cadence is seeking a Sr Education Application Engineer to create and deliver high-quality training content related to technology products. The ideal candidate will have a background in electrical engineering and hands-on experience with SystemVerilog and low-power simulation methodologies

Job Summary

  • The role involves creating and updating training lectures, labs, exams, and demos aligned with software releases.
  • Candidates must have a minimum of 2 years of experience with SystemVerilog coding and UVM methodology.
  • The position requires delivering courses in classroom or virtual settings and supporting online training customers.

Matching Summary

Match Score: 85

Cadence is seeking a Sr Education Application Engineer to create and deliver high-quality training content related to technology products. The ideal candidate will have a background in electrical engineering and hands-on experience with SystemVerilog and low-power simulation methodologies.

Skills & Requirements

Must-have

  • SystemVerilog coding experience
  • UVM methodology projects
  • Low-power simulation exposure
  • Functional safety simulation
  • Script authoring in Bash Perl Python TCL

Nice-to-have

  • Multimedia authoring tools proficiency
  • Excellent written and verbal English skills
  • Detail-oriented and well-organized approach
  • Ability to quickly analyze verification environments

Key Requirements

  • BSEE or MSEE degree required
  • Minimum 2 years SystemVerilog and UVM experience
  • Mandatory low-power and functional safety simulation experience

Work Rights

Not specified

Tailored Resume

Cover Letter