Engineer Design Verification Engineer

Analog Devices

Bangalore, India
Systemverilog and uvm
Module and system verification
Functional and code coverage
Plan and strategize to effectively verify a design (block as well as full-chip)

Job Summary

  • Plan and strategize to effectively verify a design (block as well as full-chip).
  • Employ UVM based verification methodology and use assertions, functional/code coverage, formal verification etc. to reach verification goals.
  • Expected to mentor, actively consult and/or lead junior engineers to achieve DV goals.

Matching Summary

Plan and strategize to effectively verify a design (block as well as full-chip).

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • module and system verification
  • functional and code coverage
  • testplan development
  • verification environment from ground up

Nice-to-have

  • technical mentoring junior engineers
  • proactive and result oriented
  • inter-personal and teamwork skills
  • familiarity with DSP

Key Requirements

  • 8–12 years of experience
  • B.Tech/M.Tech. in EE/ECE
  • proficient in System Verilog, UVM, C, Perl, Python
  • state-of-the-art verification techniques
  • formal verification, emulation

Work Rights

Not specified

Tailored Resume

Cover Letter