Asic Engineering Technical Lead :: Dft/mbist/atpg/scan Insertion :: Exp 12+ Years
Cisco UK
Bangalore, India
12+ years asic dft experience
Jtag protocols and scan architectures
Memory bist and boundary scan expertise
This role involves leading the implementation of Hardware Design-for-Test features to support ATE, in-system test, and diagnostics for complex Cisco silicon
Job Summary
This role involves leading the implementation of Hardware Design-for-Test features to support ATE, in-system test, and diagnostics for complex Cisco silicon.
The candidate will drive DFT requirements early in the design cycle while collaborating with front-end RTL and backend physical design teams.
Join a global team shaping groundbreaking next-generation networking chips within Cisco's Silicon One development organization.
Matching Summary
This role involves leading the implementation of Hardware Design-for-Test features to support ATE, in-system test, and diagnostics for complex Cisco silicon.
Skills & Requirements
Must-have
12+ years ASIC DFT experience
Jtag protocols and Scan architectures
Memory BIST and boundary scan expertise
ATPG and EDA tools proficiency
Gate level simulation debugging skills
Post-silicon validation and debug experience
Nice-to-have
Verilog design for custom DFT logic
DFT CAD development methodology
Test Static Timing Analysis skills
Tcl and Python scripting abilities
Collaboration with multi-functional teams
Key Requirements
Bachelor's or Master's Degree in Electrical or Computer Engineering
Minimum 10 years of relevant industry experience
Experience with TestMax, Tetramax, Tessent tool sets
Proficiency in System Verilog Logic Equivalency checking