Senior Asic Physical Design Engineer, Cache Coherent Interconnects

NVIDIA

Base: 136,000 usd - 218,500 usd for level 3 + 168,...
Hybrid
Physical design expertise
Hands-on synthesis experience
Timing analysis and floor-planning
NVIDIA is seeking a Senior ASIC Physical Design Engineer to join their CPU Cache Coherent Interconnects Design Team, focusing on the physical design of CPU on-chip interconnect networks and last-level caches. The ideal candidate should have at least five years of experience in high-performance semiconductor designs, with expertise in physical design tools and strong communication skills

Job Summary

  • As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro-architecture definition and feasibility.
  • This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
  • NVIDIA is widely considered to be one of the technology world’s most desirable employers with some of the most brilliant and hardworking people in the world working for us.

Matching Summary

Match Score: 85

NVIDIA is seeking a Senior ASIC Physical Design Engineer to join their CPU Cache Coherent Interconnects Design Team, focusing on the physical design of CPU on-chip interconnect networks and last-level caches. The ideal candidate should have at least five years of experience in high-performance semiconductor designs, with expertise in physical design tools and strong communication skills.

Salary

Base: 136,000 USD - 218,500 USD for Level 3 and 168,000 USD - 264,500 USD for Level 4; Bonus/Equity: Eligible for equity; Benefits: Eligible for benefits

Skills & Requirements

Must-have

  • physical design expertise
  • hands-on synthesis experience
  • timing analysis and floor-planning
  • industry standard physical design tools
  • liaison between logic and physical design teams
  • achieving timing area performance power goals

Nice-to-have

  • Verilog expertise
  • deep understanding of ASIC design flow
  • strong communication and interpersonal skills
  • ability to work in dynamic global team
  • creativity and autonomy

Key Requirements

  • Master’s Degree in Electrical Engineering Computer Engineering or Computer Science or equivalent experience
  • 5+ years experience in processor or related high-performance semiconductor designs
  • physical design expertise in high-frequency interconnect/cache/core design preferred
  • knowledge of RTL design verification DFT and ECO
  • not specified work authorization requirements

Work Rights

Not specified

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