Lead Design Verification Engineer

Intel Retiree Medical Plan Trust

Santa Clara, California, United States
Base: $220,920.00-311,890.00 usd; bonus/equity: st...
14+ years design verification experience
Deep expertise in interconnects and memory subsystems
Proficiency in amba chi, ace, axi, pcie, ucie, cxl protocols
This role requires deep DV expertise and strong protocol knowledge to define end-to-end verification strategy for critical chassis and interconnect IP programs

Job Summary

  • This role requires deep DV expertise and strong protocol knowledge to define end-to-end verification strategy for critical chassis and interconnect IP programs.
  • Candidates must drive convergence of simulation, formal, and emulation-based verification into unified bug hunting and coverage closure strategies.
  • The position offers a competitive compensation package including stock bonuses and comprehensive health, retirement, and vacation benefits.

Matching Summary

This role requires deep DV expertise and strong protocol knowledge to define end-to-end verification strategy for critical chassis and interconnect IP programs.

Salary

Base: $220,920.00-311,890.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • 14+ years design verification experience
  • Deep expertise in interconnects and memory subsystems
  • Proficiency in AMBA CHI, ACE, AXI, PCIe, UCIe, CXL protocols
  • Strong background in simulation and formal verification methodologies
  • Hands-on coding proficiency in SystemVerilog/UVM, C/C++, Python
  • Experience with AI-assisted development workflows

Nice-to-have

  • Mentoring senior and junior verification engineers
  • Working familiarity with RTL and physical design constraints
  • Track record of delivering high-quality silicon on schedule
  • Ability to adapt tools and methodologies as they evolve

Key Requirements

  • BS/MS in Electrical Engineering or Computer Science
  • 14+ years of relevant experience in design verification
  • Extensive background in IP DV with subsystem and SoC-level verification
  • Demonstrated experience in global functions including debug, trace, clock, power management, RAS, QoS, and security

Work Rights

Not specified

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