This role is central to Cisco's silicon quality by developing advanced DFT strategies that ensure every chip meets the highest standards for testability and reliability
Job Summary
This role is central to Cisco's silicon quality by developing advanced DFT strategies that ensure every chip meets the highest standards for testability and reliability.
You will architect and implement Test Access Mechanisms, scan chains, and Memory BIST infrastructures for complex integrated circuits while collaborating with multi-functional teams.
The position offers a hybrid work model with four days per week at Cisco's Yerevan office, fostering innovation and collaboration within the ASIC Design for Test team.
Matching Summary
This role is central to Cisco's silicon quality by developing advanced DFT strategies that ensure every chip meets the highest standards for testability and reliability.
Skills & Requirements
Must-have
MBIST design and implementation
Scan chain and TAM architecture
Test pattern generation and coverage analysis
DFT tools experience Synopsys Cadence Mentor
Scripting proficiency Tcl Python Perl
Nice-to-have
Low-power DFT strategies
Custom tool development skills
Mentoring junior engineers
IEEE 1149.1 and 1500 standards knowledge
Hybrid scan/MBIST approaches
Key Requirements
Bachelor's degree in Electrical or Computer Engineering