As a DFX Architect, you will define the overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world-class quality, minimize Test Cost (TCO), and accelerate Time-to-Market (TTM)
Job Summary
As a DFX Architect, you will define the overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world-class quality, minimize Test Cost (TCO), and accelerate Time-to-Market (TTM).
This is a high-visibility leadership role requiring collaboration with Silicon Architecture, Physical Design, and Post-Silicon Manufacturing teams across global sites.
You will drive the adoption of advanced DFX features such as IEEE 1687 (IJTAG), IEEE 1838 (3D-IC), and High-Speed Link Testing (HSLT).
Matching Summary
As a DFX Architect, you will define the overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world-class quality, minimize Test Cost (TCO), and accelerate Time-to-Market (TTM).
Skills & Requirements
Must-have
DFX architectures for multi-die systems
Advanced DFX features adoption
Test Cost Optimization strategies
On-chip debug infrastructures definition
Cross-functional influence and partnership
EDA vendor roadmap influence
Nice-to-have
Technical beacon for engineering site
Balancing technical perfection with business constraints
Resolving mission-critical silicon issues
Key Requirements
10-12 years of hands-on experience in DFT/DFD
4 years in an architectural or lead capacity
Familiar with semiconductor end-to-end product life cycle