Digital Verification Engineer

Ciena Corporation

Base: $70,700 - $112,900; bonus/equity: discretion...
System verilog uvm
Coverage-driven verification
Testbench environments and components
As a Senior Digital Verification Engineer, you will be an integral part of a team responsible for implementing innovative verification strategies for the Wavelogic family of products

Job Summary

  • As a Senior Digital Verification Engineer, you will be an integral part of a team responsible for implementing innovative verification strategies for the Wavelogic family of products.
  • You will collaborate with a team of Digital Design Engineers, Verification Engineers, and Architects to simulate and validate functional blocks and subsystems.
  • In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time.

Matching Summary

As a Senior Digital Verification Engineer, you will be an integral part of a team responsible for implementing innovative verification strategies for the Wavelogic family of products.

Salary

Base: $70,700 - $112,900; Bonus/Equity: Discretionary incentive bonus for non-sales employees; Benefits: Comprehensive benefits package

Skills & Requirements

Must-have

  • System Verilog UVM
  • coverage-driven verification
  • testbench environments and components
  • functional coverage and formal verification test plans

Nice-to-have

  • Python, Make, bash, C, C++
  • Jira and GIT
  • digital analog converters and PLLs

Key Requirements

  • Minimum Bachelor's degree in Electrical or Computer Engineering
  • Experience using System Verilog, UVM, SVA, and simulators
  • Proven ability to determine comprehensive digital verification and coverage strategies

Work Rights

Not specified

Tailored Resume

Cover Letter