Base: not specified; bonus/equity: not specified; ...
Systemverilog and uvm expertise
Advanced test bench development
Verification planning and coverage analysis
Lead verification planning and execution for complex digital and mixed-signal designs, architecting advanced verification environments and mentoring junior engineers
Job Summary
Lead verification planning and execution for complex digital and mixed-signal designs, architecting advanced verification environments and mentoring junior engineers.
Drive innovation in UVM-based verification environment development for sophisticated mixed-signal products, establishing and overseeing verification metrics including code and functional coverage goals.
Collaborate across organizational boundaries to ensure the quality and reliability of cutting-edge products, while also providing technical guidance and leading debug efforts for complex design issues.
Matching Summary
Lead verification planning and execution for complex digital and mixed-signal designs, architecting advanced verification environments and mentoring junior engineers.
Salary
Base: Not specified; Bonus/Equity: Not specified; Benefits: Not specified
Skills & Requirements
Must-have
SystemVerilog and UVM expertise
Advanced test bench development
Verification planning and coverage analysis
Scripting and automation proficiency
Complex debugging skills
Constrained random and assertion-based verification