Lead Solutions Engineer

BETA CAE Systems International AG

Multiple Locations
System verilog
Uvm based functional verification environment
Amba protocols (axi/ahb/apb)
Understand/review Design specification and develop verification strategy/Test plan/coverage plan

Job Summary

  • Understand/review Design specification and develop verification strategy/Test plan/coverage plan.
  • Writing tests/sequences/functional coverage/assertions to meet verification goals.
  • Ability and desire to learn new methodologies, languages, protocols etc.

Matching Summary

Understand/review Design specification and develop verification strategy/Test plan/coverage plan.

Skills & Requirements

Must-have

  • System Verilog
  • UVM based functional verification environment
  • AMBA protocols (AXI/AHB/APB)
  • version control software
  • load sharing software

Nice-to-have

  • Cadence tools and flows
  • ARM/CPU architectures
  • assembly language programming
  • Formal Verification experience
  • self-motivated and willing to take up additional responsibilities

Key Requirements

  • Strong background on functional verification fundamentals
  • Environment planning
  • Test plan generation
  • Environment development
  • Good knowledge of verilog/vhdl/C/C++
  • Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR
  • Strong vocabulary, communication, organizational, planning, and presentation skills

Work Rights

Not specified

Tailored Resume

Cover Letter