Functional Verification Engineer - Applied Ml

Cadence Design Systems Inc.

Formal verification experience
Systemverilog uvm expertise
Jasper xcelium eda tools
This role involves developing agentic AI solutions using Large Language Models to autonomously design and verify chips

Job Summary

  • This role involves developing agentic AI solutions using Large Language Models to autonomously design and verify chips.
  • Candidates will collaborate with machine learning engineers to train large language models at scale for semiconductor innovation.
  • The position offers the opportunity to work on cutting-edge technology with a culture that encourages creativity and impact.

Matching Summary

This role involves developing agentic AI solutions using Large Language Models to autonomously design and verify chips.

Skills & Requirements

Must-have

  • Formal verification experience
  • SystemVerilog UVM expertise
  • Jasper Xcelium EDA tools
  • Python programming skills
  • Debugging pre-silicon failures

Nice-to-have

  • Experience with LLMs and RAG
  • Knowledge of Agentic frameworks
  • Customer requirement engagement
  • Proactive problem solving approach
  • Continuous learning mindset

Key Requirements

  • BS degree with 4+ years experience OR MS with 2+ years
  • 3+ years in pre-silicon ASIC verification methodologies
  • New PhD graduate eligible

Work Rights

Not specified

Tailored Resume

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