Dft Team Leader, Hardware Engineering

Cisco UK

Bangalore, India
Dft features
Scan insertion
Bist
Lead, mentor, and develop a team of DFT engineers responsible for designing and implementing innovative DFT features ensuring high-quality, testable, and manufacturable silicon designs

Job Summary

  • Lead, mentor, and develop a team of DFT engineers responsible for designing and implementing innovative DFT features ensuring high-quality, testable, and manufacturable silicon designs.
  • Collaborate with chip architects, design engineers, and verification teams to define, optimize, and standardize DFT strategies across multiple projects.
  • Foster a culture of innovation, technical excellence, and teamwork within the DFT group.

Matching Summary

Lead, mentor, and develop a team of DFT engineers responsible for designing and implementing innovative DFT features ensuring high-quality, testable, and manufacturable silicon designs.

Skills & Requirements

Must-have

  • DFT features
  • scan insertion
  • BIST
  • boundary scan
  • ATPG
  • scan compression
  • memory BIST

Nice-to-have

  • startup-like environment
  • technical leadership
  • collaboration
  • innovation
  • system-level understanding

Key Requirements

  • BTech/Mtech. in Electrical/Computer Engineering
  • Proven hands-on experience with DFT features
  • Demonstrated experience leading engineering teams
  • Proficiency in full product lifecycle
  • Experience with ATPG methodologies
  • Ability to define and implement DFT methodologies
  • Experience leading complex technical projects

Work Rights

Not specified

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