Sr. Lead Engineer - Digital Design

NXP USA INC.

Hyderabad, India
Ai inference performance optimization
Rtl design using verilog/systemverilog
Functional verification with testbenches
The role involves defining and implementing hardware architectures optimized for AI inference performance and efficiency

Job Summary

  • The role involves defining and implementing hardware architectures optimized for AI inference performance and efficiency.
  • Candidates will develop and integrate RTL components for SoCs using industry-standard HDLs.
  • Collaboration with system engineers is essential to model workloads and analyze performance bottlenecks.

Matching Summary

The role involves defining and implementing hardware architectures optimized for AI inference performance and efficiency.

Skills & Requirements

Must-have

  • AI inference performance optimization
  • RTL design using Verilog/SystemVerilog
  • functional verification with testbenches

Nice-to-have

  • collaboration with physical design teams
  • performance bottleneck analysis
  • power optimization skills

Key Requirements

  • experience in RTL design
  • knowledge of functional verification
  • ability to collaborate with teams

Work Rights

Not specified

Tailored Resume

Cover Letter