Sr. Asic Design Engineer

Ambarella

Parma, Italy
Verilog/systemverilog module design
Logic synthesis and timing closure
Front-end methodologies and tool flows
Developing micro-architecture specifications for a next generation Computer Vision processor

Job Summary

  • Developing micro-architecture specifications for a next generation Computer Vision processor.
  • Designing and implementing Verilog/SytemVerilog modules for cutting edge SOCs, including video compression, image processing, vector processors, and device/memory controllers.
  • The company is growing and seeking a Sr. ASIC Design Engineer for their team in Parma, Italy.

Matching Summary

Developing micro-architecture specifications for a next generation Computer Vision processor.

Skills & Requirements

Must-have

  • Verilog/SystemVerilog module design
  • logic synthesis and timing closure
  • front-end methodologies and tool flows
  • hardware description languages
  • scripting languages like Python and Perl

Nice-to-have

  • Image/Video processing knowledge
  • computer vision experience
  • machine learning knowledge
  • strong communication skills
  • good team player

Key Requirements

  • Master’s degree in Electrical Engineering
  • 0-4 years of experience
  • VLSI/ASIC design understanding
  • Computer architecture understanding
  • Logic design understanding
  • Design verification knowledge
  • functional coverage knowledge

Work Rights

Not specified

Tailored Resume

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