Base: $189,300 - $271,500 (varies by location); bo...
Hybrid
Systemverilog/uvm experience
12+ years asic verification
Bachelor's or master's degree in engineering
This role involves leading the verification of highly complex ASICs used in next-generation 100G-1.6T coherent optical communications products
Job Summary
This role involves leading the verification of highly complex ASICs used in next-generation 100G-1.6T coherent optical communications products.
The successful candidate will provide technical leadership, mentor teammates, and develop process improvements in a fast-paced environment.
Cisco offers competitive compensation including base salary ranges up to $350,800 in NYC, equity grants, and comprehensive benefits packages.
Matching Summary
This role involves leading the verification of highly complex ASICs used in next-generation 100G-1.6T coherent optical communications products.
Salary
Base: $189,300 - $271,500 (varies by location); Bonus/Equity: Eligible for annual bonuses and restricted stock units; Benefits: Medical, dental, vision, 401(k) match, paid time off
Skills & Requirements
Must-have
SystemVerilog/UVM experience
12+ years ASIC verification
Bachelor's or Master's degree in Engineering
Object-oriented verification methodologies
Leading technical projects independently
Nice-to-have
C++ hybrid test benches
DSP algorithms knowledge
Formal Verification tools like Jasper
Lab silicon validation experience
Self-motivated team player
Key Requirements
12+ years of ASIC verification experience
Degree in Computer Science, Computer Engineering, or Electrical Engineering