You will be responsible for SoC architecture verification related tasks including creating test cases and test bench using UVM methodology
Job Summary
You will be responsible for SoC architecture verification related tasks including creating test cases and test bench using UVM methodology.
Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification.
Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan.
Matching Summary
You will be responsible for SoC architecture verification related tasks including creating test cases and test bench using UVM methodology.
Skills & Requirements
Must-have
UVM methodology
System Verilog language
scripting in Linux/Unix
ARM based SoC verification
protocol experience (PCIe, Ethernet, USB, TSN)
Nice-to-have
experience on Emulation
formal verification method
Perl and/or Python proficiency
Design for Debug experience
strong communication skills
flexible in dynamic environment
Key Requirements
8+ years of experience
complex ASIC designs and/or verification
experience with ARM based SoC verification
experience with protocols such as PCIe, Ethernet, USB, TSN