Sr. Asic Design Engineer

Ambarella

Base: $135,000 - $170,000; bonus/equity: new-hire ...
System verilog design and implementation
Verilog logic design and verification
Python and perl scripting proficiency
The role focuses on designing next-generation edge AI markets including automation, robotics, and intelligent low power embedded systems

Job Summary

  • The role focuses on designing next-generation edge AI markets including automation, robotics, and intelligent low power embedded systems.
  • Candidates will be responsible for synthesizing and optimizing RTL for timing, area, and power while exploring micro-architecture tradeoffs.
  • The position offers new-hire RSU grants, annual RSU opportunities, and a competitive benefits package alongside a base salary range of $135,000 to $170,000.

Matching Summary

The role focuses on designing next-generation edge AI markets including automation, robotics, and intelligent low power embedded systems.

Salary

Base: $135,000 - $170,000; Bonus/Equity: New-hire RSU grants and annual RSU grants available; Benefits: Highly competitive benefits package

Skills & Requirements

Must-have

  • System Verilog design and implementation
  • Verilog logic design and verification
  • Python and Perl scripting proficiency
  • Computer architecture knowledge
  • RTL synthesis and optimization

Nice-to-have

  • Logic synthesis and timing closure experience
  • Assembly language programming skills
  • Strong communication and teamwork
  • Adept problem-solving abilities

Key Requirements

  • Master's degree in Electrical/Electronics/Computer Engineering
  • 0-5 years of professional experience
  • Knowledge of design verification and functional coverage

Work Rights

Not specified

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