Staff Engineer, Soc Rtl Engineer

Tenstorrent

Tokyo, Japan
Not specified; not specified; highly competitive c...
On-site
Rtl development with verilog or systemverilog
Full asic flow proficiency
Power performance area optimization skills
Tenstorrent is seeking a Staff Digital Design Engineer in Tokyo to contribute to the development and optimization of high-performance chiplet-based SoC architectures. Ideal candidates will have strong expertise in digital design, RTL development, and a collaborative mindset, with opportunities to work on cutting-edge AI technology

Job Summary

  • Tenstorrent is seeking a Staff Digital Design Engineer to define, build, and optimize high-performance chiplet-based SoC architectures.
  • The role requires deep expertise in RTL development, full ASIC flows, and optimizing for power, performance, and area under aggressive goals.
  • Candidates will collaborate across design, DV, physical, and firmware teams to bring cutting-edge chiplet designs from spec to silicon.

Matching Summary

Match Score: 85

Tenstorrent is seeking a Staff Digital Design Engineer in Tokyo to contribute to the development and optimization of high-performance chiplet-based SoC architectures. Ideal candidates will have strong expertise in digital design, RTL development, and a collaborative mindset, with opportunities to work on cutting-edge AI technology.

Salary

Not specified; Not specified; Highly competitive compensation package and benefits mentioned

Skills & Requirements

Must-have

  • RTL development with Verilog or SystemVerilog
  • Full ASIC flow proficiency
  • Power performance area optimization skills
  • Computer architecture and IP microarchitecture knowledge
  • Synthesis and timing closure awareness

Nice-to-have

  • Experience with on-chip fabric and interconnect designs
  • Understanding of RISC-V Architecture
  • Debug experience in hardware design
  • Collaborative technical engineering mindset
  • Contributions to validation using emulation or FPGA

Key Requirements

  • Proficiency in HDLs such as Verilog, SystemVerilog, or VHDL
  • Prior experience in on-chip fabric and interconnect designs preferred
  • Basic understanding of RISC-V Architecture preferred
  • Eligibility to access U.S. export-controlled technology per EAR regulations

Work Rights

Must be eligible to access U.S. export-controlled technology (not D:1, E1, or E2 country nationals)

Tailored Resume

Cover Letter