Ip Design Verification Engineer

Altera Corporation

Penang, Malaysia
Not specified
Rtl design with verilog/vhdl
Linux/unix platforms
Ip-soc handoff
Altera Corporation is seeking an IP Design Verification Engineer in Penang, Malaysia. The role involves developing logic designs, coding in RTL, and ensuring the quality of integration for IP blocks in system-on-chip (SoC) designs

Job Summary

  • Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
  • Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
  • Supports SoC customers to ensure high-quality integration and verification of the IP block and drives quality assurance compliance for smooth IP-SoC handoff.

Matching Summary

Match Score: 85

Altera Corporation is seeking an IP Design Verification Engineer in Penang, Malaysia. The role involves developing logic designs, coding in RTL, and ensuring the quality of integration for IP blocks in system-on-chip (SoC) designs.

Skills & Requirements

Must-have

  • RTL design with Verilog/VHDL
  • Linux/UNIX platforms
  • IP-SoC handoff

Nice-to-have

  • advanced verification methodologies
  • constrained random verification
  • assertion based verification
  • functional coverage techniques
  • PCIe knowledge
  • Perl, C++, Java, shell scripts
  • communication skills
  • teamwork
  • highly motivated

Key Requirements

  • Bachelors or Master’s degree
  • Experienced using advanced verification methodologies
  • Familiarity or experience in RTL design
  • Familiarity or experience with RTL verification and timing analysis/closure
  • Knowledge of PCIe
  • Familiarity with Perl, C++, Java and shell scripts

Work Rights

Not specified

Tailored Resume

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