Senior Dft Timing Signoff Engineer (sta)

Intel Corporation

Folsom, California, US
Base: $164,470.00-269,100.00 usd; bonus/equity: st...
Hybrid
Primetime-based dft-mode timing constraints
Tessent dft architecture and implementation
Streaming scan network (ssn)
We are seeking a highly skilled and hands-on DFT/STA Engineer to join our full-chip timing organization supporting next-generation AI processors

Job Summary

  • We are seeking a highly skilled and hands-on DFT/STA Engineer to join our full-chip timing organization supporting next-generation AI processors.
  • Own the definition, generation, validation, and maintenance of comprehensive DFT timing constraints (SDC) in Synopsys PrimeTime for modes including Scan Shift, Scan Capture (slow/fast as applicable), JTAG/IJTAG, and Memory BIST.
  • Improve DFT/STA flows through automation (Tcl required; Python/shell preferred): multi-mode runs, report triage, regression checks, and signoff dashboards.

Matching Summary

We are seeking a highly skilled and hands-on DFT/STA Engineer to join our full-chip timing organization supporting next-generation AI processors.

Salary

Base: $164,470.00-269,100.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • PrimeTime-based DFT-mode timing constraints
  • Tessent DFT architecture and implementation
  • Streaming Scan Network (SSN)
  • IJTAG/test access integration
  • Memory test/repair (MBIST/BISR)
  • Tcl scripting

Nice-to-have

  • Python and/or shell scripting
  • cross-team closure
  • flow improvement and automation

Key Requirements

  • 8+ years in Electrical Engineering, Computer Engineering, or related field
  • 6+ years in DFT and/or STA for complex SoCs
  • Demonstrated ownership of PrimeTime-based signoff and constraints
  • Ownership of DFT-mode SDC development and PrimeTime STA signoff
  • Tessent DFT architecture concepts and integration flows
  • CDC/RDC fundamentals
  • Verilog/SystemVerilog

Work Rights

Not specified

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