5+ years system architecture design and verification
This role leads the architecture definition and technology direction for bus and payload testbed emulators supporting strategic satellite communications programs
Job Summary
This role leads the architecture definition and technology direction for bus and payload testbed emulators supporting strategic satellite communications programs.
The position requires significant expertise in hardware, software, and emulated processor technologies to guide teams through complex technical challenges.
Candidates must possess an active U.S. Secret Security Clearance and be a U.S. Person as defined by export control regulations.
Matching Summary
This role leads the architecture definition and technology direction for bus and payload testbed emulators supporting strategic satellite communications programs.
Salary
Base: $224,100 - $273,900; Bonus/Equity: Variable compensation opportunities; Benefits: Health insurance, retirement plans, paid time off
Skills & Requirements
Must-have
Active U.S. Secret Clearance required
5+ years hardware in loop validation platforms
5+ years system architecture design and verification
5+ years hardware-based testbed or STE development
5+ years C or C++ programming experience
Nice-to-have
Experience with VxWorks operating system
Familiarity with Agile or SAFe practices
PCIe I/O card H/W interface experience
Hardware/software/firmware integration skills
Strong leadership in technical risk mitigation
Key Requirements
Bachelor's degree or Higher
Active U.S. Secret Security Clearance
U.S. Citizenship required (U.S. Person)
5+ years designing hardware in the loop validation platforms